Fault Injection for TTA
The main objective of the FIT project is the experimental validation of the system concepts of TTA (Time-Triggered Architectures), taking the prototype TTP/C controller chip, developed within the ESPRIT project TTA, as the basis. EC project under the guidance of Carinthia Institute of Technology.
Project overview
- Name: Fault Injection for TTA
- Funded by: Programme for research, technological development and demonstration on a "User-friendly information society, 1998-2002" (FP5-IST)
- Number: IST-1999-10748
- Duration: 2000 - 2002
- Partners:
- Carinthia Tech Institute
- Technische Universitaet Wien
- TTTech Computertechnik GmbH, Wien
- Czech Technical University in Prague
- University of West Bohemia, Department of Computer Science and Engineering, ReliSA (formerly DSS) research group
- Universidad Politecnica de Valencia
- Chalmers University of Technology
- Motorola - Semiconductor Products Sector
- Volvo - Technological Development Corporation
- Total support: EUR 1.2 million (EUR 0.9 EU contribution)
- Staff at UWB: 3 senior researchers, 1 PhD student, 3 students
- Contact: Stanislav Racek
Fault Injection by Simulation - Workpackage 4 Solved by CTU and UWB
Our research team verified a new FT communication protocol using simulation based fault injection.
For further information, please visit http://www.fit.zcu.cz
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